The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2022

Filed:

May. 03, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Mustafa N. Kaynak, San Diego, CA (US);

William H. Radke, Los Gatos, CA (US);

Patrick R. Khayat, San Diego, CA (US);

Sivagnanam Parthasarathy, Carlsbad, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M 13/37 (2006.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01); H03M 13/11 (2006.01); H03M 13/29 (2006.01); H03M 13/15 (2006.01);
U.S. Cl.
CPC ...
H03M 13/3753 (2013.01); G06F 11/10 (2013.01); G06F 11/1012 (2013.01); G06F 11/1068 (2013.01); G11C 29/52 (2013.01); H03M 13/114 (2013.01); H03M 13/116 (2013.01); H03M 13/1111 (2013.01); H03M 13/1128 (2013.01); H03M 13/2906 (2013.01); H03M 13/3707 (2013.01); H03M 13/1108 (2013.01); H03M 13/152 (2013.01); H03M 13/1515 (2013.01);
Abstract

The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include receiving a codeword with an error correction circuit, iteratively error correcting the codeword with the error correction circuit including parity checking the codeword on a layer-by-layer basis and updating the codeword after each layer. Methods can include stopping the iterative error correction in response to a parity check being correct for a particular layer.


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