The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2022

Filed:

Nov. 13, 2020
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yu-Chi Pan, Zhubei, TW;

Ying-Liang Chuang, Zhubei, TW;

Ming-Hsi Yeh, Hsinchu, TW;

Kuo-Bin Huang, Jhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 21/28 (2006.01); H01L 21/311 (2006.01); H01L 21/8234 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42368 (2013.01); H01L 21/28185 (2013.01); H01L 27/0886 (2013.01); H01L 29/66795 (2013.01); H01L 29/7856 (2013.01); H01L 21/31122 (2013.01); H01L 21/82345 (2013.01); H01L 29/513 (2013.01);
Abstract

A semiconductor device includes a fin structure disposed over a substrate. The semiconductor device includes a first interfacial layer straddling the fin structure. The semiconductor device includes a gate dielectric layer extending along sidewalls of the fin structure. The semiconductor device includes a second interfacial layer overlaying a top surface of the fin structure. The semiconductor device includes a gate structure straddling the fin structure. The first interfacial layer and the gate dielectric layer are disposed between the sidewalls of the fin structure and the gate structure.


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