The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2022

Filed:

Sep. 04, 2020
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Kai Han, Wuhan, CN;

Yali Guo, Wuhan, CN;

Zhipeng Wu, Wuhan, CN;

Lu Zhang, Wuhan, CN;

Hang Yin, Wuhan, CN;

Simin Liu, Wuhan, CN;

Bo Xu, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 29/06 (2006.01); H01L 27/11519 (2017.01); H01L 27/11524 (2017.01); H01L 27/11556 (2017.01); H01L 27/11565 (2017.01); H01L 27/1157 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 29/0649 (2013.01);
Abstract

A memory device includes a substrate; and a stack structure, including alternately arranged first dielectric layers and electrode layers. In a first lateral direction, the memory device includes array regions and a staircase region arranged between array regions. In a second lateral direction, the stack structure includes a first block and a second block, each including a wall-structure region and extending along the first lateral direction. The wall-structure regions of the first block and the second block are adjacent to each other and together form a wall structure in the staircase region. The memory device also includes a first separation structure, formed through the stack structure and positioned between the first block and the second block in array regions along the first lateral direction; and second dielectric layers positioned between the first block and the second block in the staircase region, and alternated with the first dielectric layers.


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