The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 26, 2022

Filed:

Feb. 19, 2021
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Xinlei Jia, Wuhan, CN;

Shan Li, Wuhan, CN;

Yali Song, Wuhan, CN;

Lei Jin, Wuhan, CN;

Hongtao Liu, Wuhan, CN;

Jianquan Jia, Wuhan, CN;

XiangNan Zhao, Wuhan, CN;

Yuan-Yuan Min, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/08 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3427 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01);
Abstract

A memory device includes a memory array including memory strings. Each memory string includes a plurality of top memory cells, a plurality of bottom memory cells, and one or more dummy memory cells between the top memory cells and the bottom memory cells. The memory device also includes a plurality of word lines respectively coupled to gate terminals of the top memory cells and the bottom memory cells. The memory device further includes a control circuit configured to provide a control signal to control programming a target memory cell of the top memory cells. The gate terminal of the target memory cell are coupled to a selected word line of the word lines. The memory device further includes a word line driver coupled to the control circuit and the word lines and configured to, in response to the control signal, apply a positive first voltage signal to each of the word lines that are coupled to the gate terminals of the top memory cells during a first time period in a pre-charge phase prior to a programming phase.


Find Patent Forward Citations

Loading…