The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 12, 2022
Filed:
Nov. 23, 2020
Atomera Incorporated, Los Gatos, CA (US);
Robert John Stephenson, Duxford, GB;
Richard Burton, Phoenix, AZ (US);
Dmitri Choutov, Sunnyvale, CA (US);
Nyles Wynn Cody, Tempe, AZ (US);
Daniel Connelly, San Francisco, CA (US);
Robert J. Mears, Wellesley, MA (US);
Erwin Trautmann, San Jose, CA (US);
ATOMERA INCORPORATED, Los Gatos, CA (US);
Abstract
A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice liner at least partially covering sidewall portions of the at least one trench and defining a gap between opposing sidewall portions of the superlattice liner. The superlattice liner may include a plurality of stacked groups of layers, each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group being constrained within a crystal lattice of adjacent base semiconductor portions. The device may also include a semiconductor layer on the superlattice liner and including a dopant constrained therein by the superlattice liner, and a conductive body within the at least one trench defining a source contact.