The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2022

Filed:

Mar. 23, 2020
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Makoto Shibuya, Beppu, JP;

Kengo Aoya, Beppu, JP;

Woochan Kim, San Jose, CA (US);

Vivek Kishorechand Arora, San Jose, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/64 (2006.01); H01L 49/02 (2006.01); H01L 23/00 (2006.01); H01L 21/8234 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49844 (2013.01); H01L 21/4853 (2013.01); H01L 21/8234 (2013.01); H01L 23/49811 (2013.01); H01L 23/642 (2013.01); H01L 24/45 (2013.01); H01L 24/85 (2013.01); H01L 28/60 (2013.01); H01L 2924/13064 (2013.01);
Abstract

An integrated circuit (IC) package includes a substrate having a first region and a second region. The substrate includes a conductive path between the first region and the second region. The IC package also includes a lead frame having a first member and a second member that are spaced apart. The IC package further includes a half-bridge power module. The half-bridge power module includes a capacitor having a first node coupled to the first member of the lead frame and a second node coupled to the second member of the lead frame. The half-bridge power module also includes a high side die having a high side field effect transistor (FET) embedded therein and a low side die having a low side FET embedded therein. A source of the high side FET is coupled to a drain of the low side FET through the conductive path of the substrate.


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