The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2022

Filed:

Sep. 01, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Dae-Woo Kim, Phoenix, AZ (US);

Ajay Jain, Albuquerque, NM (US);

Neha M. Patel, Chandler, AZ (US);

Rodrick J. Hendricks, Rio Rancho, NM (US);

Sujit Sharan, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 24/16 (2013.01); H01L 23/538 (2013.01); H01L 23/5383 (2013.01); H01L 23/562 (2013.01); H01L 25/0655 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/3512 (2013.01);
Abstract

An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.


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