The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2022

Filed:

Aug. 31, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Sheng-Huang Huang, Hsinchu, TW;

Chung-Chiang Min, Zhubei, TW;

Harry-Hak-Lay Chuang, Zhubei, TW;

Hung Cho Wang, Taipei, TW;

Sheng-Chang Chen, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); G11C 5/06 (2006.01); H01L 21/3213 (2006.01); G11C 11/16 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76877 (2013.01); G11C 5/06 (2013.01); G11C 11/161 (2013.01); H01L 21/3213 (2013.01); H01L 21/76802 (2013.01);
Abstract

The present disclosure relates to a method of forming an integrated chip. The method includes forming a memory device over a substrate and forming an etch stop layer over the memory device. An inter-level dielectric (ILD) layer is formed over the etch stop layer and laterally surrounding the memory device. One or more patterning process are performed to define a first trench extending from a top of the ILD layer to expose an upper surface of the etch stop layer. A removal process is performed to remove an exposed part of the etch stop layer. A conductive material is formed within the interconnect trench after performing the removal process.


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