The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 2022

Filed:

Feb. 04, 2020
Applicant:

Globalfoundries U.s. Inc., Santa Clara, CA (US);

Inventors:

Faraz Khan, Los Angeles, CA (US);

Dan Moy, Bethel, CT (US);

Norman W. Robson, Hopewell Junction, NY (US);

Robert Katz, Hopewell Junction, NY (US);

Darren L. Anand, Williston, VT (US);

Toshiaki Kirihata, Poughkeepsie, NY (US);

Assignee:

GLOBALFOUNDRIES U.S. INC., Malta, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 27/11568 (2017.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); H01L 27/11573 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); H01L 27/11573 (2013.01); H01L 29/7923 (2013.01);
Abstract

The present disclosure generally relates to semiconductor structures and, more particularly, to charge trap memory devices and methods of manufacture and operation. The semiconductor memory includes: a charge trap transistor comprising a gate structure, a source region and a drain region; and a self-heating circuit which selectively applies an alternating bias direction between the source region and the drain region of the charge trap transistor to provide an erase operation or a programming operation of the charge trap transistor.


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