The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 14, 2022
Filed:
Jun. 23, 2020
Silicon Storage Technology, Inc., San Jose, CA (US);
Jinho Kim, Saratoga, CA (US);
Elizabeth Cuevas, Los Gatos, CA (US);
Yuri Tkachev, Sunnyvale, CA (US);
Parviz Ghazavi, San Jose, CA (US);
Bernard Bertello, Bouches du Rhones, FR;
Gilles Festes, Fuveau, FR;
Bruno Villard, Aix en Provence, FR;
Catherine Decobert, Pourrieres, FR;
Nhan Do, Saratoga, CA (US);
Jean Francois Thiery, Vaucluse, FR;
Silicon Storage Technology, Inc., San Jose, CA (US);
Abstract
A memory device includes a semiconductor substrate with memory cell and logic regions. A floating gate is disposed over the memory cell region and has an upper surface terminating in opposing front and back edges and opposing first and second side edges. An oxide layer has a first portion extending along the logic region and a first thickness, a second portion extending along the memory cell region and has the first thickness, and a third portion extending along the front edge with the first thickness and extending along a tunnel region portion of the first side edge with a second thickness less than the first thickness. A control gate has a first portion disposed on the oxide layer second portion and a second portion vertically over the front edge and the tunnel region portion of the first side edge. A logic gate is disposed on the oxide layer first portion.