The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2022

Filed:

Oct. 01, 2020
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Che-Fu Chuang, Changhua County, TW;

Jian-Ting Chen, Tainan, TW;

Yu-Kai Liao, Yunlin County, TW;

Hsiu-Han Liao, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11517 (2017.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11517 (2013.01); H01L 29/6653 (2013.01); H01L 29/66825 (2013.01); H01L 29/66969 (2013.01);
Abstract

A method for manufacturing a memory device is provided. The method includes the following steps: providing a substrate; forming a plurality of first gate structures; forming a lining layer on the substrate; forming a spacer layer on the lining layer; forming a stop layer on the spacer layer; forming a first sacrificial layer on the stop layer; removing a portion of the first sacrificial layer to expose the stop layer on the first gate structures, and to expose the stop layer at the bottoms of the trenches; removing the stop layer at the bottoms of the trenches to expose the spacer layer; removing the remaining first sacrificial layer; forming a second sacrificial layer on the substrate; and removing the second sacrificial layer, and removing the spacer layer and the lining layer at the bottoms of the plurality of trenches to expose the substrate.


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