The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2022

Filed:

May. 08, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Hsin-Yi Lee, Hsinchu, TW;

Ji-Cheng Chen, Hsinchu, TW;

Cheng-Lung Hung, Hsinchu, TW;

Weng Chang, Hsinchu, TW;

Chi On Chui, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/417 (2006.01); C23C 16/455 (2006.01); H01L 21/285 (2006.01); H01L 21/28 (2006.01); H01L 21/764 (2006.01); H01L 27/088 (2006.01); H01L 29/08 (2006.01); H01L 29/06 (2006.01); H01L 29/49 (2006.01); H01L 29/45 (2006.01); C23C 16/34 (2006.01);
U.S. Cl.
CPC ...
H01L 21/82345 (2013.01); C23C 16/34 (2013.01); C23C 16/45553 (2013.01); H01L 21/28088 (2013.01); H01L 21/28518 (2013.01); H01L 21/764 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823475 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 29/0653 (2013.01); H01L 29/0847 (2013.01); H01L 29/41791 (2013.01); H01L 29/45 (2013.01); H01L 29/4966 (2013.01); H01L 29/66545 (2013.01);
Abstract

A method includes forming isolation regions extending into a semiconductor substrate, and recessing the isolation regions. After the recessing, a portion of a semiconductor material between the isolation region protrudes higher than top surfaces of the isolation regions to form a semiconductor fin. The method further includes forming a gate stack, which includes forming a gate dielectric on sidewalls and a top surface of the semiconductor fin, and depositing a titanium nitride layer over the gate dielectric as a work-function layer. The titanium nitride layer is deposited at a temperature in a range between about 300° C. and about 400° C. A source region and a drain region are formed on opposing sides of the gate stack.


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