The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2022

Filed:

Jan. 11, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Prasoonkumar Surti, Folsom, CA (US);

Narayan Srinivasa, Portland, OR (US);

Feng Chen, Shanghai, CN;

Joydeep Ray, Folsom, CA (US);

Ben J. Ashbaugh, Folsom, CA (US);

Nicolas C. Galoppo Von Borries, Portland, OR (US);

Eriko Nurvitadhi, Hillsboro, OR (US);

Balaji Vembu, Folsom, CA (US);

Tsung-Han Lin, Campbell, CA (US);

Kamal Sinha, Rancho Cordova, CA (US);

Rajkishore Barik, Santa Clara, CA (US);

Sara S. Baghsorkhi, San Jose, CA (US);

Justin E. Gottschlich, Santa Clara, CA (US);

Altug Koker, El Dorado Hills, CA (US);

Nadathur Rajagopalan Satish, Santa Clara, CA (US);

Farshad Akhbari, Chandler, AZ (US);

Dukhwan Kim, San Jose, CA (US);

Wenyin Fu, Folsom, CA (US);

Travis T. Schluessler, Hillsboro, OR (US);

Josh B. Mastronarde, Sacramento, CA (US);

Linda L. Hurd, Cool, CA (US);

John H. Feit, Folsom, CA (US);

Jeffery S. Boles, Folsom, CA (US);

Adam T. Lake, Portland, OR (US);

Karthik Vaidyanathan, Berkeley, CA (US);

Devan Burke, Portland, OR (US);

Subramaniam Maiyuran, Gold River, CA (US);

Abhishek R. Appu, El Dorado Hills, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 1/20 (2006.01); G06F 9/455 (2018.01); G06F 9/50 (2006.01); G06N 3/04 (2006.01); G06N 3/063 (2006.01); G06N 3/08 (2006.01); G06F 8/41 (2018.01);
U.S. Cl.
CPC ...
G06T 1/20 (2013.01); G06F 9/45533 (2013.01); G06F 9/5061 (2013.01); G06F 9/5094 (2013.01); G06N 3/0445 (2013.01); G06N 3/0454 (2013.01); G06N 3/063 (2013.01); G06N 3/084 (2013.01); G06F 8/41 (2013.01); G06F 2009/45583 (2013.01);
Abstract

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type.


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