The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2022

Filed:

Nov. 08, 2018
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Juil Eom, Guri-si, KR;

Bok Kyu Choi, Yongin-si, KR;

Jae Hoon Lee, Icheon-si, KR;

Jin Woo Park, Icheon-si, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/10 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 25/105 (2013.01); H01L 23/3107 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 24/02 (2013.01); H01L 24/16 (2013.01); H01L 23/49816 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/02375 (2013.01); H01L 2224/02377 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/16235 (2013.01); H01L 2225/1058 (2013.01);
Abstract

A stack package includes a first sub-package and a second sub-package stacked on the first sub-package. The first sub-package includes a first through mold via (TMV) for connection spaced apart from a first semiconductor chip in an X-axis direction, a first TMV for bypass spaced apart from the first semiconductor chip in a Y-axis direction, and a first redistribution line (RDL) pattern connecting the first semiconductor chip to the first TMV for connection. The second sub-package includes a second TMV for connection spaced apart from a second semiconductor chip in the Y-axis direction and another RDL pattern connecting the second semiconductor chip to the second TMV for connection. the second sub-package is stacked on the first sub-package such that the second TMV for connection is connected to the first TMV for bypass.


Find Patent Forward Citations

Loading…