The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2022
Filed:
Dec. 17, 2018
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Jing-Cheng Lin, Hsinchu, TW;
Chen-Hua Yu, Hsinchu, TW;
Jui-Pin Hung, Hsinchu, TW;
Der-Chyang Yeh, Hsinchu, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/24 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 24/14 (2013.01); H01L 23/49811 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/97 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 24/13 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/24195 (2013.01); H01L 2224/97 (2013.01); H01L 2924/014 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/181 (2013.01); H01L 2924/183 (2013.01); H01L 2924/18162 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19043 (2013.01); H01L 2924/19105 (2013.01);
Abstract
A method comprises applying a metal-paste printing process to a surface-mount device to form a metal pillar, placing a first semiconductor die adjacent to the surface-mount device, forming a molding compound layer over the first semiconductor die and the surface-mount device, grinding the molding compound layer until a top surface of the first semiconductor die is exposed and forming a plurality of interconnect structures over the molding compound layer.