The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2022

Filed:

Dec. 04, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Roman W. Olac-Vaw, Hillsboro, OR (US);

Walid M. Hafez, Portland, OR (US);

Chia-Hong Jan, Portland, OR (US);

Pei-Chi Liu, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 27/12 (2006.01); H01L 21/84 (2006.01); H01L 21/28 (2006.01); H01L 23/528 (2006.01); H01L 29/49 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/82345 (2013.01); H01L 21/28088 (2013.01); H01L 21/823431 (2013.01); H01L 21/823475 (2013.01); H01L 21/823821 (2013.01); H01L 21/823842 (2013.01); H01L 21/845 (2013.01); H01L 23/5283 (2013.01); H01L 27/0886 (2013.01); H01L 27/1211 (2013.01); H01L 29/4966 (2013.01); H01L 29/7855 (2013.01); H01L 29/66545 (2013.01);
Abstract

Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.


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