The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 10, 2022
Filed:
Jul. 16, 2020
Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;
Shou-Zen Chang, Taichung, TW;
Yi-Hsung Wei, Taoyuan, TW;
Jia-You Lin, Hsinchu, TW;
Pei-Hsiu Tseng, Tainan, TW;
Chih-Peng Lee, Yunlin County, TW;
Chi-Wei Lin, New Taipei, TW;
Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;
Abstract
A SRAM device includes a substrate, at least one two-transistor static random access memory (2T-SRAM), an inner dielectric layer, a plurality of contacts, an inter-layer dielectric (ILD) layer, a plurality of vias, and a conductive line. The 2T-SRAM is disposed on the substrate, the inner dielectric layer covers the 2T-SRAM, and the contacts are disposed in the inner dielectric layer and coupled to the 2T-SRAM. The ILD layer covers the inner dielectric layer and the contacts, and the vias are disposed in the ILD layer and respectively coupled to the 2T-SRAM trough the corresponding contacts. The conductive line is disposed on the ILD layer and connects with the plurality of vias, wherein the thickness of the conductive line is less than or equal to one-tenth of the thickness of the via such that it can significantly reduce the coupling effect compared with the traditional bit line.