The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 19, 2022
Filed:
Jun. 17, 2020
Method of designing a layout, method of making a semiconductor structure and semiconductor structure
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Gulbagh Singh, Hsinchu, TW;
Chih-Ming Lee, Tainan, TW;
Chi-Yen Lin, Tainan, TW;
Wen-Chang Kuo, Tainan, TW;
C. C. Liu, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A method of designing a layout includes determining a first layout pattern, wherein the first layout pattern corresponds to a plurality of contact pads. The method further includes generating a second layout pattern. The method further includes checking whether an edge of the second layout pattern overlaps the first layout pattern. The method further includes adjusting the second layout pattern so that the edge of the second layout pattern overlaps the first layout pattern in response to a determination that the edge of the second layout pattern is separated from the first layout pattern.