The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 2022
Filed:
Jan. 17, 2020
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Inventors:
Xusheng Wu, Hsinchu, TW;
Chang-Miao Liu, Hsinchu, TW;
Ying-Keung Leung, Hsinchu, TW;
Huiling Shang, Hsinchu County, TW;
Youbo Lin, Ridgefield, CT (US);
Assignee:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 21/768 (2006.01); H01L 21/283 (2006.01); H01L 29/45 (2006.01); H01L 21/285 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/401 (2013.01); H01L 21/283 (2013.01); H01L 21/28518 (2013.01); H01L 21/76802 (2013.01); H01L 21/76831 (2013.01); H01L 21/76877 (2013.01); H01L 29/456 (2013.01); H01L 29/665 (2013.01);
Abstract
A method including providing a device including a gate structure and a source/drain feature adjacent to the gate structure. An insulating layer (e.g., CESL, ILD) is formed over the source/drain feature. A trench is etched in the insulating layer to expose a surface of the source/drain feature. A semiconductor material is then formed in the etched trench on the surface of the source/drain feature. The semiconductor material is converted to a silicide.