The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2022

Filed:

Sep. 19, 2019
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Anna Maria Conti, Milan, IT;

Agostino Pirovano, Milan, IT;

Andrea Redaelli, Casatenovo, IT;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2481 (2013.01); H01L 27/2409 (2013.01); H01L 27/2427 (2013.01); H01L 45/1675 (2013.01);
Abstract

A method of forming an array of memory cells, where the array comprises an elevationally-inner tier of memory cells comprising spaced-inner-tier-lower-first-conductive lines and inner-tier-programmable material directly there-above, an elevationally-outer tier of memory cells comprising spaced-outer-tier-lower-first-conductive lines and outer-tier-programmable material directly there-above, and spaced-upper-second-conductive lines that are electrically shared by the outer-tier memory cells and the inner-tier memory cells, comprises depositing conductor material for all of the shared-spaced-upper-second-conductive lines. All of the conductor material for all of the shared-spaced-upper-second-conductive lines is patterned using only a single masking step. Other method embodiments and arrays of memory cells independent of method of manufacture are disclosed.


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