The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 05, 2022
Filed:
Apr. 04, 2018
Intel Corporation, Santa Clara, CA (US);
Stephen Christianson, Tigard, OR (US);
Stephen Hall, Forest Grove, OR (US);
Emile Davies-Venn, Gilbert, AZ (US);
Dong-Ho Han, Beaverton, OR (US);
Kemal Aygun, Tempe, AZ (US);
Konika Ganguly, Portland, OR (US);
Jun Liao, Hillsboro, OR (US);
M. Reza Zamani, Hillsboro, OR (US);
Cory Mason, Hillsboro, OR (US);
Kirankumar Kamisetty, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Techniques for fabricating a package substrate and/or a stiffener for a semiconductor package are described. For one technique, a package substrate comprises: a routing layer comprising a dielectric layer. A stiffener may be above the routing layer and a conductive line may be on the routing layer, the conductive line comprising first and second portions, the first portion having a first width, the second portion having a second width, the conductive line extending from a first region of the routing layer to a second region of the routing layer, the first region being under the stiffener, the second region being outside the stiffener, the first portion being on the first region, and the second portion being on the second region. One or more portions of the conductive line can be perpendicular to an edge of the stiffener. The perpendicular portion(s) may comprise a transition between the first and second widths.