The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2022

Filed:

Mar. 29, 2019
Applicant:

Intel Corporaiton, Santa Clara, CA (US);

Inventors:

Brinda Ganesh, Portland, OR (US);

Yen-Cheng Liu, Portland, OR (US);

Swadesh Choudhary, Mountain View, CA (US);

Tejpal Singh, Hudson, MA (US);

Pradeep Prabhakaran, Holden, MA (US);

Monam Agarwal, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/173 (2006.01); G06F 15/76 (2006.01); G06F 15/80 (2006.01); G06F 13/40 (2006.01); G06F 115/08 (2020.01);
U.S. Cl.
CPC ...
G06F 15/17381 (2013.01); G06F 13/4027 (2013.01); G06F 15/8023 (2013.01); G06F 2115/08 (2020.01);
Abstract

In one embodiment, a system on chip includes: a plurality of intellectual property (IP) agents formed on a semiconductor die; a mesh interconnect formed on the semiconductor die to couple the plurality of IP agents, and a plurality of mesh stops each to couple one or more of the plurality of IP agents to the mesh interconnect. The mesh interconnect may be formed of a plurality of rows each having one of a plurality of horizontal interconnects and a plurality of columns each having one of a plurality of vertical interconnects;, where at least one of the plurality of rows includes an asymmetrical number of mesh stops. Other embodiments are described and claimed.


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