The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 15, 2022
Filed:
Mar. 12, 2019
Embedded component package structure, embedded type panel substrate and manufacturing method thereof
Applicant:
Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;
Inventors:
Yu-Ju Liao, Kaohsiung, TW;
Chien-Fan Chen, Kaohsiung, TW;
Chien-Hao Wang, Kaohsiung, TW;
I-Chia Lin, Kaohsiung, TW;
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC., Kaohsiung, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H05K 1/186 (2013.01); H01L 21/4857 (2013.01); H01L 23/49822 (2013.01); H01L 24/03 (2013.01); H01L 24/06 (2013.01); H01L 2224/24137 (2013.01);
Abstract
An embedded component package structure including a circuit substrate, an embedded component and a stress compensation layer is provided. The circuit substrate includes a core layer and an asymmetric circuit structure, and the core layer has a first thickness. The embedded component is disposed in the core layer. The stress compensation layer is disposed on one side of the core layer, and the stress compensation layer has a second thickness between 4 μm and 351 μm.