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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11276645 B1

PDFFull Text
Date of Patent:
Mar. 15, 2022

Filed:

Aug. 19, 2020

Encapsulation of a substrate electrically connected to a plurality of pin arrays

Applicant:

Huawei Technologies Co., Ltd., Shenzhen, CN;

Inventors:

Nan Zhao, Shenzhen, CN;

Wenxu Xie, Shenzhen, CN;

Junlei Tao, Shenzhen, CN;

Shanghsuan Chiang, Shenzhen, CN;

HuiLi Fu, Shenzhen, CN;

Assignee:

HUAWEI TECHNOLOGIES CO., LTD., Shenzhen, CN;

Attorney:

Maier & Maier, PLLC

Primary Examiner:

Alonzo Chambliss

Int. Cl.
CPC ...
H01L 23/12 (2006.01); H01L 23/34 (2006.01); H01L 23/48 (2006.01); H01L 21/00 (2006.01); H01L 21/44 (2006.01); H05K 7/20 (2006.01); H05K 1/00 (2006.01); H05K 7/00 (2006.01); H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5381 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/563 (2013.01); H01L 23/3185 (2013.01); H01L 23/3675 (2013.01); H01L 23/49811 (2013.01); H01L 23/49816 (2013.01); H01L 23/5383 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 23/562 (2013.01); H01L 24/14 (2013.01); H01L 24/16 (2013.01); H01L 25/50 (2013.01); H01L 2224/1403 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/3511 (2013.01);
Abstract

A chip and a packaging method thereof. In the chip, first solder pads in a first solder pad array on a first substrate are attached to corresponding second pins in second pin arrays on different dies to implement short-distance and high-density interconnection of the different dies. A molding body is used to wrap a first pin, a second pin, a first solder pad, and the first substrate, so that a fan-out unit and the first substrate are molded into an integral structure. In the integral structure, bottoms of first pins that are in a first pin array on a die and that are electrically connected to a periphery of the chip are not wrapped by the molding body.

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