The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2022

Filed:

Aug. 30, 2020
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hua-Hsin Yu, Hsinchu, TW;

Cheng-Hung Lee, Hsinchu, TW;

Hung-Jen Liao, Hsin-Chu, TW;

Hau-Tai Shieh, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4091 (2006.01); G11C 11/4074 (2006.01); G11C 11/4076 (2006.01); G11C 11/4099 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4091 (2013.01); G11C 7/106 (2013.01); G11C 7/1087 (2013.01); G11C 11/4074 (2013.01); G11C 11/4076 (2013.01); G11C 11/4099 (2013.01);
Abstract

The disclosure is directed to a memory circuit, an electronic device, and a method of operating the memory circuit. According to an exemplary embodiment, the disclosure is directed to a memory circuit which includes not limited to a voltage equalizing circuit configured to equalize and pre-charge a first data line and a second data line to a reference voltage, a sense amplifier circuit configured to sense a binary data based on a relative voltage between the first data line and the second data line, a read-out latch circuit configured to receive the binary data which is to be transmitted to an external controller, and a write circuit configured to receive a first signal of the first data line and a second signal of the second data line so as to write the first signal to a first bit line and the second signal to a second bit line.


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