The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2022

Filed:

Aug. 05, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Saurabh Sharma, El Dorado Hills, CA (US);

Abhishek Venkatesh, Hillsboro, OR (US);

Travis T. Schluessler, Hillsboro, OR (US);

Prasoonkumar Surti, Folsom, CA (US);

Altug Koker, El Dorado Hills, CA (US);

Aravindh V. Anantaraman, Folsom, CA (US);

Pattabhiraman P. K., Bangalore, IN;

Abhishek R. Appu, El Dorado Hills, CA (US);

Joydeep Ray, Folsom, CA (US);

Kamal Sinha, Rancho Cordova, CA (US);

Vasanth Ranganathan, El Dorado Hills, CA (US);

Bhushan M. Borole, Rancho Cordova, CA (US);

Wenyin Fu, Folsom, CA (US);

Eric J. Hoekstra, Latrobe, CA (US);

Linda L. Hurd, Cool, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 1/20 (2006.01); G06T 1/60 (2006.01); G06T 15/00 (2011.01);
U.S. Cl.
CPC ...
G06T 1/20 (2013.01); G06T 1/60 (2013.01); G06T 15/005 (2013.01);
Abstract

A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.


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