The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 22, 2022
Filed:
Sep. 17, 2019
Applicant:
Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;
Inventors:
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC., Kaohsiung, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 25/16 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/14 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/17 (2013.01); H01L 24/81 (2013.01); H01L 24/94 (2013.01); H01L 24/97 (2013.01); H01L 2224/1146 (2013.01); H01L 2224/11845 (2013.01); H01L 2224/1357 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13564 (2013.01); H01L 2224/13565 (2013.01); H01L 2224/13582 (2013.01); H01L 2224/13583 (2013.01); H01L 2224/13611 (2013.01); H01L 2224/13639 (2013.01); H01L 2224/13647 (2013.01); H01L 2224/13655 (2013.01); H01L 2224/1403 (2013.01); H01L 2224/1412 (2013.01); H01L 2224/14505 (2013.01); H01L 2224/17505 (2013.01); H01L 2224/8183 (2013.01); H01L 2224/81143 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/81906 (2013.01);
Abstract
A semiconductor package structure includes a semiconductor die surface having a narrower pitch region and a wider pitch region adjacent to the narrower pitch region, a plurality of first type conductive pillars in the narrower pitch region, each of the first type conductive pillars having a copper-copper interface, and a plurality of second type conductive pillars in the wider pitch region, each of the second type conductive pillars having a copper-solder interface. A method for manufacturing the semiconductor package structure described herein is also disclosed.