The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2022

Filed:

Mar. 27, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Praneeth Kumar Akkinepally, Tempe, AZ (US);

Frank Truong, Gilbert, AZ (US);

Jason M. Gamba, Gilbert, AZ (US);

Robert Alan May, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 25/065 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5381 (2013.01); H01L 23/3157 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01); H01L 25/0655 (2013.01);
Abstract

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a microelectronic component embedded in the package substrate, the microelectronic component including: a substrate having a surface, where the substrate includes a conductive pathway and a mold material region at the surface, where the mold material region includes a through-mold via (TMV) electrically coupled to the conductive pathway, and where the mold material region is at the second surface of the package substrate; and a die conductively coupled, at the second surface of the package substrate, to the package substrate and to the TMV of the microelectronic component.


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