The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 18, 2022

Filed:

Nov. 05, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Chun-Yuan Chen, Tainan, TW;

Ching-Chun Wang, Tainan, TW;

Dun-Nian Yaung, Taipei, TW;

Hsiao-Hui Tseng, Tainan, TW;

Jhy-Jyi Sze, Hsin-Chu, TW;

Shyh-Fann Ting, Tainan, TW;

Tzu-Jui Wang, Fengshan, TW;

Yen-Ting Chiang, Tainan, TW;

Yu-Jen Wang, Kaohsiung, TW;

Yuichiro Yamashita, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/00 (2006.01); H01L 27/146 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1463 (2013.01); H01L 27/1464 (2013.01); H01L 27/14643 (2013.01); H01L 27/14689 (2013.01); H01L 27/14609 (2013.01); H01L 27/14621 (2013.01); H01L 27/14627 (2013.01);
Abstract

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an image sensing element disposed within a semiconductor substrate. One or more isolation structures are arranged within one or more trenches disposed along a first surface of the semiconductor substrate. The one or more isolation structures are separated from opposing sides of the image sensing element by non-zero distances. The one or more trenches are defined by sidewalls and a horizontally extending surface of the semiconductor substrate. A doped region is laterally arranged between the sidewalls of the semiconductor substrate defining the one or more trenches and is vertically arranged between the image sensing element and the first surface of the semiconductor substrate.


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