The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 18, 2022

Filed:

Jul. 25, 2019
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Jerry Chang Jui Kao, Taipei, TW;

Hui-Zhong Zhuang, Kaohsiung, TW;

Yung-Chen Chien, Hsinchu, TW;

Ting-Wei Chiang, New Taipei, TW;

Chih-Wei Chang, Hsinchu, TW;

Xiangdong Chen, San Diego, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/327 (2020.01); H01L 25/00 (2006.01); H03K 19/00 (2006.01);
U.S. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/392 (2020.01); H01L 25/00 (2013.01); G06F 30/327 (2020.01); G06F 30/394 (2020.01); H03K 19/00 (2013.01);
Abstract

A multi-bit standard cell embodied on a non-transitory computer-readable medium includes: a first logic cell with a first logic cell height measured from a first lower boundary to a first upper boundary of the first logic cell; and a second logic cell with a second logic cell height measured from a second lower boundary to a second upper boundary of the second logic cell, the second logic cell height different from the first logic cell height, and the second upper boundary attached to the first lower boundary. The first logic cell is arranged to perform a first logical function, the second logic cell is arranged to perform a second logical function, and the first logical function is the same as the second logical function.


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