The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 11, 2022
Filed:
Apr. 12, 2020
Applicant:
Mediatek Inc., Hsin-Chu, TW;
Inventors:
Yao-Chun Su, Hsinchu, TW;
Chih-Jung Hsu, Hsinchu, TW;
Yi-Jou Lin, Hsinchu, TW;
I-Hsuan Peng, Hsinchu, TW;
Assignee:
MEDIATEK INC., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/00 (2006.01); H01L 23/58 (2006.01); H01L 23/66 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5386 (2013.01); H01L 23/3128 (2013.01); H01L 23/3675 (2013.01); H01L 23/5385 (2013.01); H01L 23/562 (2013.01); H01L 23/585 (2013.01); H01L 23/66 (2013.01); H01L 25/0655 (2013.01); H01L 2223/6638 (2013.01); H01L 2223/6666 (2013.01);
Abstract
An electronic package configured to operate at Gigabit-per-second (Gbps) data rates is disclosed. The electronic package includes a package substrate of a rectangular shape. A chip package having a first high-speed interface circuit die is mounted on a top surface of the package substrate. The chip package is rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through about 45 degrees. The first high-speed interface circuit die includes a first Serializer/Deserializer (SerDes) circuit block.