The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 2022

Filed:

Apr. 05, 2018
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Jungrae Park, Santa Clara, CA (US);

Wei-Sheng Lei, San Jose, CA (US);

Brad Eaton, Menlo Park, CA (US);

James S. Papanu, San Rafael, CA (US);

Ajay Kumar, Cupertino, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/544 (2006.01); A47G 19/22 (2006.01); B65D 47/24 (2006.01); B65D 47/32 (2006.01); B23K 26/0622 (2014.01); B23K 10/00 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 23/544 (2013.01); A47G 19/22 (2013.01); A47G 19/2272 (2013.01); B23K 10/003 (2013.01); B23K 26/0624 (2015.10); B65D 47/244 (2013.01); B65D 47/32 (2013.01); H01L 21/78 (2013.01); H01L 2223/5446 (2013.01);
Abstract

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a split laser beam laser scribing process, such as a split shaped laser beam laser scribing process, to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.


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