The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 2022

Filed:

Nov. 19, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Shao-Ming Koh, Hsinchu, TW;

Chen-Ming Lee, Taoyuan County, TW;

I-Wen Wu, Hsinchu, TW;

Fu-Kai Yang, Hsinchu, TW;

Jia-Heng Wang, Hsinchu, TW;

Mei-Yun Wang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 29/78 (2006.01); H01L 27/06 (2006.01); H01L 21/02 (2006.01); H01L 21/324 (2006.01); H01L 21/768 (2006.01); H01L 23/535 (2006.01); H01L 27/092 (2006.01); H01L 29/08 (2006.01); H01L 29/16 (2006.01); H01L 29/161 (2006.01); H01L 29/167 (2006.01); H01L 29/45 (2006.01); H01L 29/165 (2006.01); H01L 29/66 (2006.01); H01L 21/306 (2006.01); H01L 21/3065 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823871 (2013.01); H01L 21/02063 (2013.01); H01L 21/324 (2013.01); H01L 21/76805 (2013.01); H01L 21/76814 (2013.01); H01L 21/76831 (2013.01); H01L 21/76889 (2013.01); H01L 21/76895 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 23/535 (2013.01); H01L 27/0605 (2013.01); H01L 27/0924 (2013.01); H01L 29/0847 (2013.01); H01L 29/16 (2013.01); H01L 29/161 (2013.01); H01L 29/167 (2013.01); H01L 29/1608 (2013.01); H01L 29/45 (2013.01); H01L 29/7845 (2013.01); H01L 29/7848 (2013.01); H01L 21/3065 (2013.01); H01L 21/30604 (2013.01); H01L 21/823807 (2013.01); H01L 29/165 (2013.01); H01L 29/665 (2013.01); H01L 29/66545 (2013.01); H01L 29/7843 (2013.01);
Abstract

A method includes providing a structure that includes a substrate, a first gate structure and a second gate structure over the substrate, and a first source/drain (S/D) feature and a second S/D feature over the substrate. The first S/D feature is adjacent to the first gate structure, the second S/D feature is adjacent to the second gate structure, the first S/D feature is configured for an n-type transistor, and the second S/D feature is configured for a p-type transistor. The method further includes introducing a p-type dopant into both the first and the second S/D features. After the introducing of the p-type dopant, the method further includes performing an etching process to the first and the second S/D features, wherein the etching process etches the first S/D feature faster than it etches the second S/D feature.


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