The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 2022

Filed:

Dec. 12, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Wen-Sheh Huang, Hsinchu, TW;

Hsiu-Wen Hsueh, Taichung, TW;

Yu-Hsiang Chen, Hsinchu, TW;

Chii-Ping Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/762 (2006.01); H01L 27/06 (2006.01); H01L 21/311 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76898 (2013.01); H01L 21/31105 (2013.01); H01L 21/762 (2013.01); H01L 21/76811 (2013.01); H01L 27/0629 (2013.01); H01L 28/24 (2013.01);
Abstract

A method for forming a semiconductor device is provided. The method includes forming a dielectric layer over a semiconductor substrate and forming a conductive line in the dielectric layer. The method also includes forming an etch stop layer over the dielectric layer and the conductive line and patterning the etch stop layer to form a contact opening exposing a portion of the conductive line. The method further includes forming a resistive layer over the etch stop layer, wherein the resistive layer extends into the contact opening. In addition, the method includes patterning the resistive layer to form a resistive element.


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