The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 28, 2021

Filed:

May. 22, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chen-Hua Yu, Hsinchu, TW;

Wei Ling Chang, Hsinchu, TW;

Chuei-Tang Wang, Taichung, TW;

Chieh-Yen Chen, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 25/18 (2006.01); H01L 23/498 (2006.01); H01L 23/48 (2006.01); H01L 25/16 (2006.01); H01L 23/31 (2006.01); H01L 25/00 (2006.01); H01L 23/00 (2006.01); H01L 21/78 (2006.01); H01L 21/56 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 21/486 (2013.01); H01L 21/4857 (2013.01); H01L 21/56 (2013.01); H01L 21/78 (2013.01); H01L 23/3128 (2013.01); H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 24/19 (2013.01); H01L 24/24 (2013.01); H01L 24/25 (2013.01); H01L 25/16 (2013.01); H01L 25/50 (2013.01); H01L 2224/24145 (2013.01); H01L 2224/24225 (2013.01); H01L 2224/2518 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1434 (2013.01);
Abstract

In an embodiment, a structure includes: a graphics processor device; a passive device coupled to the graphics processor device, the passive device being directly face-to-face bonded to the graphics processor device; a shared memory device coupled to the graphics processor device, the shared memory device being directly face-to-face bonded to the graphics processor device; a central processor device coupled to the shared memory device, the central processor device being directly back-to-back bonded to the shared memory device, the central processor device and the graphics processor device each having active devices of a smaller technology node than the shared memory device; and a redistribution structure coupled to the central processor device, the shared memory device, the passive device, and the graphics processor device.


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