The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 21, 2021

Filed:

Jun. 25, 2018
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chia-Ao Chang, Jinhu Township, TW;

Chien-Hao Chen, Chuangwei Township, TW;

De-Wei Yu, Ping-tung, TW;

Yung-Cheng Lu, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 21/762 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/76283 (2013.01); H01L 21/823431 (2013.01); H01L 29/4966 (2013.01); H01L 29/6656 (2013.01); H01L 29/66636 (2013.01);
Abstract

Embodiments disclosed herein relate generally to forming a structure, e.g., in high aspect ratio trenches. In an embodiment, a method for semiconductor processing is provided. The method includes forming fins on a substrate. Sidewalls of the fins and a bottom surface between the sidewalls of the fins define a trench therebetween. The method includes forming a gate structure over the fins. The gate structure has a sidewall with a defect region formed therein. The method includes forming a filling layer to fill the defect region in the sidewall of the gate structure.


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