The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 14, 2021

Filed:

Sep. 03, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chansyun David Yang, Shinchu, TW;

Han-Yu Lin, Nantou, TW;

Chun-Yu Chen, Hsinchu, TW;

Chih-Ching Wang, Jinhu Township, TW;

Fang-Wei Lee, Hsinchu, TW;

Tze-Chung Lin, Hsinchu, TW;

Li-Te Lin, Hsinchu, TW;

Gwan-Sin Chang, Hsinchu, TW;

Pinyen Lin, Rochester, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 29/417 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/785 (2013.01); H01L 21/823431 (2013.01); H01L 29/0673 (2013.01); H01L 29/41791 (2013.01); H01L 29/66795 (2013.01); H01L 2029/7858 (2013.01); H01L 2924/13086 (2013.01); Y10S 977/938 (2013.01);
Abstract

The current disclosure describes techniques for forming a gate-all-around device where semiconductor layers are released by etching out the buffer layers that are vertically stacked between semiconductor layers in an alternating manner. The buffer layers stacked at different vertical levels include different material compositions, which bring about different etch rates with respect to an etchant that is used to remove at least partially the buffer layers to release the semiconductor layers.


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