The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 14, 2021

Filed:

Jan. 07, 2020
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Choonghyun Lee, Rensselaer, NY (US);

Alexander Reznicek, Troy, NY (US);

Xin Miao, Slingerlands, NY (US);

Richard Glen Southwick, III, Halfmoon, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 21/8234 (2006.01); H01L 21/3065 (2006.01); H01L 21/02 (2006.01); H01L 27/088 (2006.01); H01L 21/764 (2006.01); H01L 21/306 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7827 (2013.01); H01L 21/0217 (2013.01); H01L 21/3065 (2013.01); H01L 21/764 (2013.01); H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 21/823437 (2013.01); H01L 21/823462 (2013.01); H01L 21/823481 (2013.01); H01L 21/823487 (2013.01); H01L 27/088 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/495 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/6656 (2013.01); H01L 21/30625 (2013.01);
Abstract

A method of forming a vertical transport field-effect transistor (VFET) is provided. The method includes forming vertical fin channels by etching part way through a substrate. The method further includes forming a bottom source/drain electrode partially into the substrate and beneath the vertical fin channels. A gate dielectric layer is then formed on the vertical fin channels. A gate conductor layer is then formed on the gate dielectric layer. A height of the gate conductor layer is less than a height of the vertical fin channels. The method further includes forming a spacer layer on a top surface of the gate conductor layer. The method also includes forming a top source/drain electrode on a top surface of the vertical fin channels. A gap exists between the top source/drain electrode and the spacer layer.


Find Patent Forward Citations

Loading…