The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 14, 2021

Filed:

Dec. 29, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kevin Lin, Beaverton, OR (US);

Christopher J. Jezewski, Portland, OR (US);

Richard F. Vreeland, Hillsboro, OR (US);

Tristan A. Tronic, Aloha, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 27/01 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5228 (2013.01); H01L 21/76816 (2013.01); H01L 21/76831 (2013.01); H01L 27/016 (2013.01); H01L 28/24 (2013.01);
Abstract

Methods/structures of forming thin film resistors using interconnect liner materials are described. Those methods/structures may include forming a first liner in a first trench, wherein the first trench is disposed in a dielectric layer that is disposed on a substrate. Forming a second liner in a second trench, wherein the second trench is adjacent the first trench, forming an interconnect material on the first liner in the first trench, adjusting a resistance value of the second liner, forming a first contact structure on a top surface of the interconnect material, and forming a second contact structure on the second liner.


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