The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 07, 2021

Filed:

Oct. 24, 2019
Applicant:

Globalfoundries U.s. Inc., Santa Clara, CA (US);

Inventors:

Jagar Singh, Clifton Park, NY (US);

Luigi Pantisano, Saratoga Springs, NY (US);

Anvitha Shampur, Malta, NY (US);

Frank Scott Johnson, Saratoga Springs, NY (US);

Srikanth Balaji Samavedam, Cohoes, NY (US);

Assignee:

GlobalFoundries U.S. Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 27/092 (2006.01); H01L 21/761 (2006.01); H01L 21/8234 (2006.01); H01L 29/423 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7816 (2013.01); H01L 21/761 (2013.01); H01L 21/823481 (2013.01); H01L 21/823493 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 21/823892 (2013.01); H01L 27/0924 (2013.01); H01L 29/0646 (2013.01); H01L 29/0653 (2013.01); H01L 29/42376 (2013.01); H01L 29/66659 (2013.01); H01L 29/66681 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

A semiconductor device is disclosed including a semiconductor layer, a first well doped with dopants of a first conductivity type defined in the semiconductor layer, a second well doped with dopants of a second conductivity type different than the first conductivity type defined in the semiconductor layer adjacent the first well to define a PN junction between the first and second wells, and an isolation structure positioned in the second well. The semiconductor device also includes a first source/drain region positioned in the first well, a second source/drain region positioned in the second well adjacent a first side of the isolation structure, a doped region positioned in the second well adjacent a second side of the isolation structure, and a gate structure positioned above the semiconductor layer, wherein the gate structure vertically overlaps a portion of the doped region.


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