The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 07, 2021

Filed:

Aug. 29, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Hung-Li Chiang, Taipei, TW;

Chao-Ching Cheng, Hsinchu, TW;

Chih-Liang Chen, Hsinchu, TW;

Tzu-Chiang Chen, Hsinchu, TW;

Ta-Pen Guo, Taipei, TW;

Yu-Lin Yang, Hsinchu County, TW;

I-Sheng Chen, Taipei, TW;

Szu-Wei Huang, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 27/11 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823814 (2013.01); H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/823807 (2013.01); H01L 21/823878 (2013.01); H01L 27/092 (2013.01); H01L 27/1104 (2013.01); H01L 29/0653 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01); H01L 27/1108 (2013.01); H01L 29/0673 (2013.01);
Abstract

In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.


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