The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 23, 2021
Filed:
Aug. 27, 2020
Silicon Storage Technology, Inc., San Jose, CA (US);
Jinho Kim, Saratoga, CA (US);
Xian Liu, Sunnyvale, CA (US);
Feng Zhou, Fremont, CA (US);
Parviz Ghazavi, San Jose, CA (US);
Steven Lemke, Boulder Creek, CA (US);
Nhan Do, Saratoga, CA (US);
Silicon Storage Technology, Inc., San Jose, CA (US);
Abstract
A method of forming a semiconductor device where memory cells and some logic devices are formed on bulk silicon while other logic devices are formed on a thin silicon layer over insulation over the bulk silicon of the same substrate. The memory cell stacks, select gate poly, and source regions for the memory devices are formed in the memory area before the logic devices are formed in the logic areas. The various oxide, nitride and poly layers used to form the gate stacks in the memory area are formed in the logic areas as well. Only after the memory cell stacks and select gate poly are formed, and the memory area protected by one or more protective layers, are the oxide, nitride and poly layers used to form the memory cell stacks removed from the logic areas, and the logic devices are then formed.