The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 23, 2021

Filed:

Mar. 19, 2018
Applicant:

The 13th Research Institute of China Electronics Technology Group Corporation, Hebei, CN;

Inventors:

Jia Li, Shijiazhuang, CN;

Weili Lu, Shijiazhuang, CN;

Yulong Fang, Shijiazhuang, CN;

Jiayun Yin, Shijiazhuang, CN;

Bo Wang, Shijiazhuang, CN;

Yanmin Guo, Shijiazhuang, CN;

Zhirong Zhang, Shijiazhuang, CN;

Zhihong Feng, Shijiazhuang, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/04 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/045 (2013.01); H01L 21/0217 (2013.01); H01L 21/02211 (2013.01); H01L 21/02271 (2013.01); H01L 21/02378 (2013.01); H01L 21/02381 (2013.01); H01L 21/02529 (2013.01); H01L 21/02634 (2013.01);
Abstract

The disclosure provides a method for passivating a silicon carbide epitaxial layer, relating to the technical field of semiconductors. The method includes the following steps: introducing a carbon source and a silicon source into a reaction chamber, and growing a silicon carbide epitaxial layer on a substrate; and turning off the carbon source, introducing a nitrogen source and a silicon source into the reaction chamber, and growing a silicon nitride thin film on an upper surface of the silicon carbide epitaxial layer. The silicon nitride thin film grown by the method has few defects and high quality, and may be used as a lower dielectric layer of a gate electrode in a field effect transistor. It does not additionally need an oxidation process to form a SiOdielectric layer, thereby reducing device fabrication procedures.


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