The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 2021

Filed:

Jun. 10, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Sheng-Yu Wu, Hsinchu, TW;

Ching-Hui Chen, Hsinchu, TW;

Mirng-Ji Lii, Hsinchu County, TW;

Kai-Di Wu, Tainan, TW;

Chien-Hung Kuo, Tainan, TW;

Chao-Yi Wang, Tainan, TW;

Hon-Lin Huang, Hsinchu, TW;

Zi-Zhong Wang, Tainan, TW;

Chun-Mao Chiu, Kaohsiung, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/13 (2013.01); H01L 24/08 (2013.01); H01L 24/11 (2013.01); H01L 2224/1147 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13155 (2013.01); H01L 2924/13091 (2013.01);
Abstract

A semiconductor device comprises a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump over the conductive pad, a conductive cap over the conductive bump, and a passivation layer over the semiconductor substrate and surrounding the conductive bump. A combination of the conductive bump and the conductive cap has a stepped sidewall profile. The passivation layer has an inner sidewall at least partially facing and spaced apart from an outer sidewall of the conductive bump.


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