The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 2021

Filed:

Jul. 09, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kiran C. Veernapu, Bangalore, IN;

Kamlesh Pillai, Bangalore, IN;

James Valerio, Hillsboro, OR (US);

Joydeep Ray, Folsom, CA (US);

Abhishek Appu, El Dorado Hills, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/48 (2006.01); G06F 9/54 (2006.01); G06T 15/00 (2011.01); G06T 1/20 (2006.01); G06F 9/22 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4881 (2013.01); G06F 9/22 (2013.01); G06F 9/54 (2013.01); G06T 1/20 (2013.01); G06T 15/005 (2013.01);
Abstract

A mechanism is described to facilitate microcontroller-based flexible thread scheduling launching in computing environments. An apparatus of embodiments, as described herein, includes facilitating a graphics processor hosting a microcontroller having a thread scheduling unit, and detection and observation logic to detect a scheduling algorithm associated with an application at the apparatus. The apparatus may further include reading and dispatching logic to facilitate the microcontroller to prepare a flexible dispatch routine based on the scheduling algorithm. The apparatus may further include scheduling and launching logic to facilitate the thread scheduling unit to dynamically schedule and launch threads based on the flexible dispatch routine, where the threads are hosted by the graphics processor.


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