The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 02, 2021

Filed:

Sep. 30, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Son Nguyen, Schenectady, NY (US);

Takeshi Nogami, Schenectady, NY (US);

Thomas Jasper Haigh, Jr., Claverack, NY (US);

Cornelius Brown Peethala, Slingerlands, NY (US);

Matthew T. Shoudy, Guilderland, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 21/02 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76835 (2013.01); H01L 21/02126 (2013.01); H01L 21/02167 (2013.01); H01L 21/02203 (2013.01); H01L 21/7682 (2013.01); H01L 21/76837 (2013.01); H01L 21/76852 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/5329 (2013.01); H01L 23/53209 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H01L 23/53252 (2013.01); H01L 23/53266 (2013.01);
Abstract

A method includes forming a metallic interconnect structure on a semiconductor substrate where the metallic interconnect structure comprises a plurality of metal lines with adjacent metal lines separated by a gap therebetween. The method further includes selectively depositing a first low-k dielectric material onto the semiconductor substrate and onto exposed surfaces of the metal lines of the metallic interconnect structure to form a barrier on at least the metal lines. The barrier is configured to minimize oxidation and diffusion of metal of the metal lines. The method also includes depositing a flowable second low-k dielectric material onto the semiconductor substrate to form a dielectric layer encapsulating the barrier and the metallic interconnect structure.


Find Patent Forward Citations

Loading…