The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 26, 2021
Filed:
Oct. 10, 2019
Globalfoundries U.s. Inc., Santa Clara, CA (US);
Steven M. Shank, Jericho, VT (US);
Anthony K. Stamper, Williston, VT (US);
Siva P. Adusumilli, South Burlington, VT (US);
Ian McCallum-Cook, Burlington, VT (US);
Michel J. Abou-Khalil, Essex Junction, VT (US);
GLOBALFOUNDRIES U.S. INC., Santa Clara, CA (US);
Abstract
Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. Shallow trench isolation regions extend from a top surface of a semiconductor substrate into the semiconductor substrate. The semiconductor substrate contains single-crystal semiconductor material, and the shallow trench isolation regions are positioned to surround an active device region of the semiconductor substrate. A polycrystalline layer is formed in the semiconductor substrate. The polycrystalline layer has a first section beneath the active device region and a second section beneath the plurality of shallow trench isolation regions. The first section of the polycrystalline layer is located at a different depth relative to the top surface of the semiconductor substrate than the second section of the polycrystalline layer.