The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 19, 2021
Filed:
Jun. 15, 2020
Shanghai Huali Integrated Circuit Corporation, Shanghai, CN;
Jhencyuan Li, Shanghai, CN;
Yingju Chen, Shanghai, CN;
Liyao Liu, Shanghai, CN;
Chanyuan Hu, Shanghai, CN;
Shanghai Huali Integrated Circuit Corporation, Shanghai, CN;
Abstract
This disclosure discloses a process method for cutting a polysilicon gate of a FinFET transistor, comprising: step, forming a fin and a first groove in a polysilicon gate formation region and forming a second groove in a non-polysilicon gate region; step, performing filing with a first insulating layer; step, performing definition by using a second photomask opposite to a first photomask that defines a polysilicon gate cutting region, and forming a first mask on the top of the first insulating layer in the second groove; step, performing etching-back of the first insulating layer to define the height of the fin; step, forming a polysilicon gate; and step, after the polysilicon gate cutting region is opened by using the first photomask, performing polysilicon etching to achieve cutting of the polysilicon gate. In the present disclosure, the process window is enlarged, thereby increasing the product yield.