The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 12, 2021
Filed:
Nov. 30, 2019
Intel Corporation, Santa Clara, CA (US);
Ayan Kar, Portland, OR (US);
Kalyan C. Kolluru, Portland, OR (US);
Nicholas A. Thomson, Hillsboro, OR (US);
Mark Armstrong, Portland, OR (US);
Sameer Jayanta Joglekar, Hillsboro, OR (US);
Rui Ma, Portland, OR (US);
Sayan Saha, Portland, OR (US);
Hyuk Ju Ryu, Portland, OR (US);
Akm A. Ahsan, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Disclosed herein are transistor arrangements of field-effect transistors with dual thickness gate dielectrics. An example transistor arrangement includes a semiconductor channel material, a source region and a drain region, provided in the semiconductor material, and a gate stack provided over a portion of the semiconductor material that is between the source region and the drain region. The gate stack has a thinner gate dielectric in a portion that is closer to the source region and a thicker gate dielectric in a portion that is closer to the drain region, which may effectively realize tunable ballast resistance integrated with the transistor arrangement and may help increase the breakdown voltage and/or decrease the gate leakage of the transistor.