The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 12, 2021

Filed:

Feb. 19, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Wei-Yu Chen, New Taipei, TW;

An-Jhih Su, Taoyuan, TW;

Li-Hsien Huang, Hsinchu County, TW;

Tien-Chung Yang, Hsinchu, TW;

Ming-Shih Yeh, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/10 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/105 (2013.01); H01L 21/4857 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 23/49822 (2013.01); H01L 24/05 (2013.01); H01L 24/16 (2013.01); H01L 25/50 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/16235 (2013.01);
Abstract

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die an insulating encapsulation laterally covering the semiconductor die. The semiconductor die includes a semiconductor substrate, a plurality of conductive pads distributed over the semiconductor substrate, a plurality of conductive vias disposed on and electrically connected to the conductive pads, and a dielectric layer disposed over the semiconductor substrate and spaced the conductive vias apart from one another. A sidewall of the dielectric layer extends along sidewalls of the conductive vias, the conductive vias are recessed from a top surface of the dielectric layer, and a sloped surface of the dielectric layer is connected to the top surface of the dielectric layer and the sidewall of the dielectric layer.


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